Coils integrated in IC-package

ABSTRACT

Method for providing at least one inductance associated with a chip attached to a support, in which said inductances are provided by means of at least a first bondwire having first and second ends. In which method said first end of said first bondwire is bonded to a first pad on said chip by means of an automated process using the chip as a reference for placing the first end of the first bondwire on the first pad when bonding it thereto. The second end of said first bondwire is bonded to a second pad on said support by means of the automated process using the chip as a reference for placing the second end of the first bondwire on the second pad when bonding it thereto.

[0001] The present application is a divisional application ofapplication Ser. No. 09/684,950, filed Oct. 10, 2000, the contents ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a method for providing at leastone inductance associated with a chip attached to a support, in whichsaid inductances are provided by means of at least a first bondwirehaving first and second ends, and in which said first end of said firstbondwire is bonded to a first pad on said chip by means of an automatedprocess using the chip as a reference for placing the first end of thefirst bondwire on the first pad when bonding it thereto.

[0003] Integrated circuit packages usually consist of at least onesemiconductor chip, which is often referred to as a die, and electricalconductors providing the communication to the exterior. The chip ismounted on a support, e.g., an interposer or a lead-frame, by means ofgluing or a similar fastening method. To finish the package, theassembly of chip, support and electrical conductors, is moulded in bymeans of an appropriate plastic material, thus sealing the assembly andleaving only terminals in the form of pads or pins protruding to theexterior. Alternatively the sealing can be made by fastening a covermade of plastic, a ceramic material, or some other appropriate material,to the support.

[0004] The electrical conductors providing the communication to theexterior, are usually made from gold or aluminum threads, which are atone end connected to terminal pads on the chip, and at the other endconnected to metal plated pads on the support, the pads themselves beingconnected to the exterior in some manner. These threads are commonlyreferred to as bondwires.

[0005] All conductors, and thus also the bondwires, exhibit aninductance. However, since the bondwires are relatively short, theirinductance is so small that it is not of importance at low frequencies.For this reason the inductance of the bondwires has largely beenignored.

[0006] In connection with chips working at radio frequencies (RF), orotherwise designed for RF applications, the inductances cannot beignored. This gives the circuit designer the choice of either minimizingthe inductive effect of the bondwires, or deliberately target theinductance of the bondwires for the use as a circuit component.

[0007] The use of bondwires to provide specific inductances, issuggested in the article “A I 0.8 GHz CMOS Low-Phase-NoiseVoltage-Controlled Oscillator with Prescaler”, Craninckx, J. andSteyaert, M. S. J., IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 30, No.12, December 1995, pages 1474 to 1482. The article states that to beable to predict the inductance value as correctly as possibly the lengthof the bond wires must be controlled accurately, because the length ofthe bondwire is the main factor determining its inductance. As asolution the article suggests the use of on-chip bond wires.

[0008] U.S. Pat. No. 886,393 also deals with the use of bondwires forproviding an inductance. In this patent the bondwires are looped aroundbetween pads on the chip or the support to form a coil. The problem ofinductance precision is not dealt with in the patent.

[0009] The use of on-chip bondwires provides quite predictable resultsbecause the pads are situated on the chip and their relative positionthus fixed with the high accuracy of the chip manufacturing process.Since the distance between the pads is well known, the length ofbondwire, and thus the inductance, is predictable.

[0010] The on-chip approach though, has one major drawback, namely howto bond the second end of the bondwire to the chip. Ends of bondwiresare normally connected to pads using one of two methods, ball-bondingand wedge-bonding. Ball-bonding is normally used to bond the first endof the bondwire to a pad on the chip, wedge-bonding is normally used tobond the second end of the bondwire to a pad on the support. Awedge-bond places considerable stress on the pad, and is normally notconsidered suitable for use on the chip. Thus, if a wedge-bond is usedto connect the second end of the bondwire to the chip, specialprecautions must be taken not to damage the chip. If a ball-bond is usedthe procedure is quite complicated, the wire must be severed and endheated to form a ball, then the end must be placed on the pad andbonded. The procedure of making a second ball-bond is so complicatedthat it rarely, if ever, is used for mass production. Either way thismakes the approach expensive.

[0011] Another drawback of placing all the pads are on the chip, is thatthey take up a large portion of the chip area, which is then wasted.

[0012] Placing all bondwire inductors on another surface with morerugged pads 20 leaves the problem of connecting the inductor.

[0013] In a hybrid solution where some of the pads are placed on thechip and others on another surface inside of the IC package, e.g. on thesupport, the value of the inductors becomes less predictable.

[0014] This is due to the fact that the positioning of the chip on thesupport in the IC package, using standard production methods, has muchwider tolerances than the positioning of a pad on the chip. Thistolerance is compensated for by the bondwire.

[0015] The way this compensation is effected is that when the first endof the bondwire is placed on the pad on the chip the positioning is donerelative to the chip, whereas when the second end of the bondwire isplaced on the pad on the support this is done relative to the support.

[0016] In this way the positioning of both ends of the bondwire iscorrect, with regard to the respective pad to which it is attached, evenif the position of the chip on the support deviates from one IC packageto another.

[0017] The result being that the tolerances on the positioning of thechip on the support in the IC package is reflected in the length of thebondwires and thus in their inductance, the inductance of a bondwirebeing roughly 1 Nh/mm.

SUMMARY OF THE INVENTION

[0018] According to a first aspect of the invention there is establisheda method for providing at least one inductance associated with a chipattached to a support, in which said inductances are provided by meansof at least a first bondwire having first and second ends, and in whichsaid first end of said first bondwire is bonded to a first pad on saidchip by means of an automated process using the chip as a reference forplacing the first end of the first bondwire on the first pad whenbonding it thereto, characterized in that said second end of said firstbondwire is bonded to a second pad on said support by means bf theautomated process using the chip as a reference for placing the secondend of the first bondwire on the second pad when bonding it thereto. Theobject of the present invention is to overcome the above problems inproviding well defined inductances associated with a chip.

[0019] In other words, according to the invention the problems outlinedabove are solved by placing the first end of the bondwire on the chipand the second end of the bondwire on the support and positioning bothends of the bonding wire relative to the chip. In order to use the chipas a reference of both ends of the bonding wire, it is however necessaryto enlarge the connection pads on the support accordingly so as tocompensate for the tolerances.

[0020] According to a second aspect of the invention there is providedan integrated circuit package including a chip, a support to which thechip is attached, and at least one bondwire extending from a first padon the chip to a second pad on the support and electrically connectingthe first and the second pads, characterized in that the smallestdimension on the second pad is at least six times the diameter of thebondwire.

[0021] Thus, with the invention, the length of the bondwire remains thesame from one IC package to another, but in the different IC packagesthe second end of the bondwire will be positioned in different places onthe respective pad on the support to which it is attached. The onlycompromise necessary is the use of enlarged connection pads, butenlarging these pads will not pose any problems, since usually the ICpackage, and in particular the supporting surface for the enlargedconnection pads is much larger than the chip itself, thus providingample room for the bondwires.

[0022] Further the support is much less expensive, compared to the chip,because the support basically is comparable with a printed circuitboard, whereas the chip itself is a high precision semiconductor part.

[0023] The invention will now be explained in greater detail by means ofa non-limiting exemplary embodiment, and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 schematically shows a cross section of a chip and a supportconnected by bondwires. In the preferred embodiment the support has theform of an interposer.

[0025]FIG. 2 schematically shows a top plan view of a chip and aninterposer connected by bondwires.

DETAILED DESCRIPTION OF THE INVENTION

[0026] In FIG. 1 there is schematically shown a cross section of an ICpackage 1. The package I includes a chip 2, which is mounted on ainterposer 3. In the preferred embodiment the chip 2 is glued to anupper surface of the support 3, by means of glue 4.

[0027] After the chip 2 has been glued to the upper surface of theinterposer 3 electrical connections are formed between the chip 2 andthe interposer 3. The electrical connections are formed by means ofbondwires 5 which are at their one end attached to pads 6 on the chip,and at their other to pads 7 on the interposer 3.

[0028] The bondwires 5 are usually gold or aluminium threads, with adiameter of approximately 25-50 μm. Typically the pads 6 on the chip 2to which the bondwires are attached are squares with a side length ofabout 3 times the diameter of the bondwire 5. The precision with whichbondwire is attached to the pads 6 on the chip 2 is typically +1-10˜m onboth the X and the Y coordinate.

[0029] Finally after the bondwires 5 have been attached, the wholeassembly of chip 2, bondwires S and interposer 3, or at least the uppersurface thereof, are moulded in by means of an appropriate plasticmaterial 8. Connections from the pads 7 to the exterior is provided bymeans of vias 9, which electrically connect the pads 7 to pads 10 on thelower surface of the interposer 3. The vias 9 are metal plated throughholes in the insulating board acting as base material for theinterposer.

[0030] The pads 10 on the lower side of the may be terminals for input,output or ground etc.

[0031] Eventually when the IC package I is mounted on a printed circuitboard (not shown) of a device, electrical connections are made by meansof soldering, conductive glue or the like between the pads 10 andcorresponding pads on the printed circuit board.

[0032]FIG. 2 schematically shows a perspective top view of a chip 2mounted on an interposer 3 and connected electrically connected theretoby means of bondwires 5 from pads 6 on the chip to pads 11, 12, 13 onthe interposer 3.

[0033] As indicated earlier, the present invention deals with theinevitable inductances of the bondwires 5, and in particular with how tocontrol the inductance value of the bondwires 5, because these cannot beneglected in RF applications.

[0034] In FIG. 2 there is shown various types of connections between thechip 2 and the interposer 3 may be formed.

[0035] Some of the connections, such as e.g. the connections from thechip 2 to the 30 pads 11 or 12 may be deliberately targeted for the useas inductances in the RF application of the chip 2, whereas others 13may constitute connections where an inductance is not desired yetinevitable.

[0036] In either case it is of great interest to know the value of theinductance with 5 the greatest possible precision in order be able totake it into account a priori when designing the chip 2.

[0037] In the exemplary case shown, the two bondwire connections fromdifferent pads 6 on the chip 2 to a common pad 12, form a loop togetherwith the pad 12 itself, and thus basically provide a one turn coil.

[0038] As will be seen plural bondwires 5 connect pads 6 on the chip 2to a large contact area or pad 11. Each of these bondwires may form aninductance. These inductances may largely be independent of each othersbecause the contact area 11 constitutes ground or RF ground.

[0039] It should however be noticed that the vias 9 can be omitted incertain cases, e.g., if a loop such as the one associated with pad 12 isformed, the pad 12 need not have a via to the other side of the carrier.

[0040] It should further be noted, that even though not shown in thefigures it is possible draw a bondwire 5 from the pad 6 on the chip 2 toa pad 7, 11, 12, 13 on via one or more intermediate pads. i.e., drawinga first length of bondwire 5 to the intermediate pad, and subsequentlydrawing a second length of bondwire 5 to a pad 13, where the connectionto the exterior is made. In this case the pad 13 may be associated witha via, whereas the intermediate pad need not.

[0041] Using several intermediate pads it is further possible to formlarger loop coils between two pads 6 on the chip, than possible whenusing only one pad 12, as will be described below.

[0042] Conventionally the chip 2 is placed on the interposer 3 by meansof an automated process, e.g., using a robot. In order not to increasecosts this is done with much less precision compared to the precision inthe bonding process. A typical value for the precision with which thechip 2 is placed on the interposer 3 is +/−150μ.

[0043] Both of these tolerances are far more coarse than the precisionof position of the pads 6 relative to the chip 2. This is due to thefact that the precision on the pads 6 relative to the chip 2 isdetermined with the same high precision with which the remainingpatterns are manufactured on the chip 2.

[0044] When the chip 2 has been placed on the interposer 3 and gluedthereto, the bonding takes place, in an automated bonding machine. Thebonding machine is program controlled.

[0045] In order to accurately place the first end of the bondwire on therespective pad 6 on the chip 2, the pattern recognition uses arecognizable pattern on the chip 2. This may be a pattern consisting ofa number of the pads 6 themselves, or it may be a specific purpose maderecognizable pattern. The pattern being provided with the same precisionon the chip 2 as the pads 6.

[0046] The bondwire 5 is then drawn to the desired pad 7, 11, 12, 13 onthe interposer 3, where it is attached and severed.

[0047] According to the invention the pads 7, 11, 12, 13 on theinterposer 3 have sizes which allow the bonding machine to attach thesecond end of a predetermined length of bondwire 5 to them, even if theposition of the chip 2 on the interposer 3 is off-set from a nominalposition. i.e., if the chip 2 is placed off-set from a nominal position,the desired length of wire may still be drawn in the predetermineddirection towards the pad 7, 11, 12, 13 on the interposer 3 and attachedto this pad 7, 11, 12, 13. In the applications contemplated the typicallength of the bondwire 5 is 0.5-2 mm, but the invention is of course notlimited to such lengths.

[0048] Since, as mentioned above, the precision with which the chip 2 isplaced on 10 the interposer 3 is approximately +/−150μ and the thicknessof the bondwire is approximately 25-50μ, the pads 7, 11, 12, 13 on theinterposer must at least have a smallest dimension of approximately300μ, corresponding to at least six times the diameter of the bondwire5. However, preferably the lower diameter of 25μ for the bondwire 5 isused and the smallest dimension on the pads 7, 11, 12, 13 should thus beat least twelve times the diameter of the bondwire 5. However it isfurther desired to have some additional margin on the tolerances it ismore preferred that the smallest dimension on the pads 7, 11, 12, 13 isat least fifteen times the thickness of the bondwire 5.

[0049] This allows the bonding machine to use only one reference, namelythe one on the chip 2, and still attach the bondwires on the pads 6, 11,12, 13 on the interposer 3. i.e., it may attach the bondwires inaccordance with their predetermined configuration resulting in thedesired lengths based on a nominal position of the chip 2, because evenif the chip 2 deviates in its position from the desired predeterminedposition on the interposer 3, the attachment point of the second end ofthe bondwire 4 will still be within the area of the pads 7, 11, 12, 13on the interposer 3. The attachment point of the second end of thebondwire 5 is then off-set from its nominal attachment point on the pads7, 11, 12, 13 with an amount corresponding to the off-set of the chip 2on the interposer 3.

[0050] The enlarged areas of the pads 7, 11, 12, 13 on the interposer 3,however, do not influence the inductances substantially.

[0051] Further they can be provided at low cost, because space on theinterposer is not so costly as on the chip.

[0052] Hence bondwire inductances with precise values may be provided atlower costs than it is possible with the on-chip solutions of the priorart. For the attachment of the bondwires 5 to the chip 2 and theinterposer 3 any conventional process may be employed e.g., ultrasonicbonding, thermo-compression bonding, such as ball-bonding orwedge-bonding, any hybrid thereof.

[0053] The fact that all first ends of all wires are attached to thepads 6 on the chip 2, and all second ends are attached to the pads 7,11, 12, 13 on the interposer 3, provides the further advantage that thefirst free end of the bondwire 5 can be attached to the chip withoutrisk of damaging it. The bondwire 5 can then be attached to the pads 7,11, 12, 13 on the interposer 3 and severed, so as to provide a new freeend. The severing action, which may be a pressing and scraping action,is of no risk of damaging the chip, because it only takes place on theinterposer 3. The risk of damaging the pads 7, 11, 12, 13 on theinterposer 3 in the severing action is less pronounced, because the pads7, 11, 12, 13 are larger and substantially more rugged than the pads 6on the chip 2.

[0054] The invention is not limited to the above described and in thedrawings shown examples of an embodiment but can be varied within thescope of the appended claims.

What is claimed is:
 1. Method for providing at least one inductanceassociated with a chip attached to a support, in which said inductancesare provided by means of at least a first bondwire having first andsecond ends, and in which said first end of said first bondwire isbonded to a first pad on said chip by means of an automated processusing the chip as a reference for placing the first end of the firstbondwire on the first pad when bonding it thereto, wherein said secondend of said first bondwire is bonded to a second pad on said support bymeans of the automated process using the chip as a reference for placingthe second end of the first bondwire on the second pad when bonding itthereto.
 2. Method according to claim 1, wherein the second end of saidat first bondwire is severed by scraping on the second pad on saidsupport.
 3. Method according to claim 2, wherein the second padconstitutes a pad which is electrically connected to the exterior of theintegrated circuit package.
 4. Method according to claim 1, wherein afirst end of a second bondwire is bonded to a third pad on said chip,and that a second end of said second bondwire is bonded to the secondpad on the support by an automated process using the chip as a referencefor placing the first and second bondwires on the second and third pads,respectively, when bonding them thereto.
 5. Method according to claim 1,wherein a first end of a second bondwire is bonded to the second pad onthe support, and that a second end of said second bondwire is bonded toa fourth pad on the support by an automated process, using the chip as areference for placing first and second bondwires to the second andfourth pads, respectively, when bonding them thereto.
 6. Methodaccording to claim 5, wherein the fourth pad constitutes a pad which iselectrically connected to the exterior of the integrated circuitpackage.
 7. Method according to claim 5, wherein the support has atleast one connector, and that the fourth pad is electrically connectedto a fifth pad on the opposite side of the support by means of thisconnector.
 8. Method according to claim 7, wherein the fifth pad is onthe outside of the integrated circuit package.
 9. Method according toclaim 2, wherein a first end of a second bondwire is bonded to a thirdpad on said chip, and that a second end of said second bondwire isbonded to the second pad on the support by an automated process usingthe chip as a reference for placing the first and second bondwires onthe second and third pads, respectively, when bonding them thereto. 10.Method according to claim 2, wherein a first end of a second bondwire isbonded to the second pad on the support, and that a second end of saidsecond bondwire is bonded to a fourth pad on the support by an automatedprocess, using the chip as a reference for placing first and secondbondwires to the second and fourth pads, respectively, when bonding themthereto.
 11. Method according to claim 6, wherein the support has atleast one connector, and that the fourth pad is electrically connectedto a fifth pad on the opposite side of the support by means of thisconnector.